In advanced processes (gate lengths of 0.35 .mu.m or less), the need has recently arisen to integrate HV transistors in high-speed devices which use the technique of saliciding the diffusions. As is known, this technique is based on the use of a layer of self-aligned silicide ("salicide"), which reduces the resistivity of the junctions. The salicide layer (typically of titanium, but also cobalt or another transition metal) is obtained by depositing a titanium layer on the entire surface of the device, and performing a heat treatment that makes the titanium react with the silicon, which is left bare on the junctions and the gate regions, such as to form titanium silicide. Subsequently, the non-reacted titanium (for example that deposited on oxide regions), is removed by etching with an appropriate solution, which leaves the titanium silicide intact. Thereby, both the gate regions and the junctions have in parallel a layer of silicide with low resistivity (approximately 3-4 .OMEGA./square), which makes it possible to reduce the resistance in series at the transistors. The salicide technique is described for example in the article "Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxide-semiconductor and complementary metal-oxide-semi-conductor technologies" by R. A. Haken, in J. Vac. Sci. Technol. B, vol. 3, No. 6, Nov/Dec 1985.
The HV transistors are formed without intensive implanting doping ionic species, to obtain lightly doped junctions, which thus have a high breakdown voltage. The saliciding process is difficult if the silicon beneath is lightly doped, and this means that it is necessary to avoid saliciding the junctions of the HV transistors.
Process flows are thus being designed which permit integration of HV transistors and LV transistors with saliciding; however this integration is made difficult by the fact that these components have different characteristics, and require different process steps.